Low-Voltage and Low-Noise CMOS Analog Circuits Using Scaled Devices

Recently low-voltage and low-noise analog circuits with sub100nm CMOS devices are strongly demanded for implementing mobile digital multimedia and wireless systems. Reduction of supply voltage makes it difficult to attain a signal voltage swing, and device deviation causes large DC offset voltage and 1/f noise. This paper describes noise reduction technique for CMOS analog and RF circuits operated at a low supply voltage below 1V. First, autozeroing and chopper stabilization techniques without floating analog switches are introduced. The amplifier test chip with a 0.18μm CMOS was measured at a 0.6V supply, and achieved 89nV/√Hz input referred noise (@100Hz). Secondly, in RF frequency range, to improve a phase noise of voltage controlled oscillator (VCO), two 1/fnoise reduction techniques are described. The ring VCO test chip achieves 1GHz oscillation, -68dBc/Hz at 100kHz offset, 710μW power dissipation at 1V power supply.